Advanced packaging technology plays more and more important role for device miniaturization, system integration, and performance enhancement. Among many new packaging technologies, fan-out panel level packaging (FOPLP) aroused more interests and showed the advantages of higher number of I/O, integration flexibilities, low cost, and small form factor due to the elimination of substrate. However, FOPLP using epoxy mold compound (EMC) material faces a number of technical challenges such as warpage panel

handling, difficult to fabricate fine-pitch redistribution layer (RDL), and reliability issues for large package due to the CTE mismatch between chip and EMC. In addition, for high performance SIP, advanced FOPLP with multilayer fine-pitch RDLs, excellent alignment accuracy, shortest interconnect routing between dies, and ultra small form factor was required.

About all the advantage and challenge mentioned above，we have great experience of FOPLP on equipment., while，we also have actual application in Korea and U.S.A，so hope to share the technology to China semiconductor industry.